Methods of dispersing an electric field may be significant in analog high voltage processes and/or high power processes. When electrically isolating semiconductor devices use a field oxide film, leakage currents and/or breakdown due to biasing of an electric field may produce complications.
Analog high voltage processes may electrically isolate logic devices from each other and protects logic devices from electric fields applied to a drain extension region of a high voltage device. Method of manufacturing isolation layer patterns in semiconductor devices using LOCOS processes may be implemented.
As illustrated in FIGS. 1A through 1CA, semiconductor substrates may be divided into high voltage device formation region HV and low voltage device formation region LV. An active region and an isolation region may be formed in high voltage device formation region HV and low voltage device formation region LV. Pad oxide film 11 may be formed over semiconductor substrate 10. Pad nitride film 12 may be formed over pad oxide film 11. A photo resist layer may be coated over pad nitride film 12. A photo resist layer may be patterned (e.g. by a photo process such as a photographic process and a developing process) to form photo resist pattern 13 over pad nitride film 12. First isolation region 14a and second isolation region 14b may have openings at high voltage device formation region HV and at low voltage device formation region LV with the same size.
As illustrated in FIG. 1B, pad nitride film 12 may be patterned using photo resist layer pattern 13 as an etch mask to expose pad oxide film 11 at first isolation region 14a and second isolation region 14b. As illustrated in FIG. 1C, pad oxide film 11 may be oxidized by an oxidizing process to form first field oxide film pattern 15a and second field oxide film pattern 15b at first isolation region 14a and second isolation region 14b. A “bird's beak” formation may be formed at each edge of first field oxide firm pattern 15a and second field oxide film pattern 15b. First field oxide film pattern 15a and second field oxide film pattern 15b may have substantially the same shape and/or same size. Photo resist layer pattern 13 may be removed. A transistor for a high voltage device may be formed at high voltage device formation region HV. A transistor for a low voltage device may be formed at low voltage device formation region LV.
When forming a first field oxide film pattern in a high voltage device formation region and a second field oxide film pattern in a low voltage device formation region that have substantially the same size and shape, complication may arise. For example, a low voltage device which requires a relatively small design rule may be compromised by second field oxide film pattern having a relatively large size.